CS222 Lecture: Introduction to the VAX: VAX Machine Language 8/12/91
Programming Using Register Absolute, Immediate revised 1/6/97
and Relative Addressing Modes
Materials: Transparencies of VAX Architecture p. 109, 97
Copy of Architecture pp. 98-99
Handout of key information
I. The Basic Architecture of A VAX
A. Although VAX computers differ widely in internal organization, they can
all be regarded as having the following basic architecture.
_________________________
| CPU |
| _____ _____ |
| |R0 | |PSL| |
| |---| ----- |
| |R1 | |
| |---| |
| .... |
| |R15| |
| ----- |
|_______________________|
|
| BUS
____________|____________
| |
| ________|________
IO DEVICES | |
| MEMORY |
|_______________|
B. IO Devices will be discussed later and vary widely from installation to
installation.
C. Memory is some number of 8 bit bytes addressed 0, 1, 2 ...
1. The VAX known as Faith has 128 MBytes of physical memory; the
workstations each have 16 MB.
2. Special hardware and software gives the user the appearance of a much
larger VIRTUAL MEMORY by using disk as an extension of main memory to
hold regions not currently being used.
3. The user view of memory is 4 Gigabytes, with addresses ranging from
00000000 to FFFFFFFF (hex). This is divided into four regions or
SPACES on the basis of the two high order bits of the address.
TRANSPARENCY: VAX Architecture p. 109
(Note that one space is always unused)
4. Individual regions of memory may be PROTECTED - e.g. all of system
space is protected against ordinary users writing to it and some is
protected against even being read by ordinary users.
5. Though memory is addressed at the byte level, data may be transferred
in units of several different sizes.
a. 1 byte
b. 1 word (2 bytes)
c. 1 longword (4 bytes)
d. 1 quadword (8 bytes)
These transfers can be done most efficiently - i.e. in a single
memory cycle - if the data is ALIGNED on an address that is
divisible by 2 (for words), 4 (for longwords) or 8 (for quadwords).
(Note: Alignment like this is not required on the VAX, but is required
by some other types of system.)
D. The CPU is where we will focus most of our attention
1. The CPU can be implemented in many different ways - e.g.
a. VAX 11/780 (original VAX model; Gordon had one until 1990) - 20
circuit boards, each 8" x 15"
b. All of our current VAXen use a single chip about one inch square.
2. The CPU has 17 user-visible registers (plus several seen only by the
operating system).
a. 16 General Registers (R0 .. R15) - each 32 bits wide
These are not all truly general - some have special functions - e.g.
i. R15 is the Program Counter (PC)
ii. R14 is the Stack Pointer (SP)
iii. R13 is the Frame Pointer (FP)
iv. R12 is the Argument Pointer (AP)
v. R0 .. R5 are used in special ways by some instructions
b. One Processor Status Longword (PSL) - also 32 bits - consisting of a
16 bit Processor Status Word (PSW) + other bits
TRANSPARENCY - ARCHITECTURE P. 97 -cf Kapps and Stafford pp. 523-524
- Go over all PSW bits and mode bits from copy of Architecture 98-99
II. VAX Instruction Format
A. All VAX instructions have the following basic format: a one or two byte
op-code, followed by 0-5 operand specifiers. (The number of operand
specifiers needed depends on the op-code - e.g. HALT needs none; a data
movement instruction generally needs two (source, destination) etc.
[ op code ] [ operand specifier ]
(0 .. 5 of these)
B. Each operand specifier is 1 to 17 bytes long
1. The first byte has the following format:
7 4 3 0
______________
| MODE | REG |
--------------
a. The 4-bit mode specifier specifies one of 16 addressing modes that
we will be learning. We will learn three now and the rest later.
b. The 4-bit register specifier generally specifies one of the 16
general registers. (Note that register 15 is the PC, which results
in some special cases.)
2. The number of remaining bytes depends on the mode.
3. The following are some of the VAX's addressing modes. You will note
that several of the modes we learn now require REG = F (15 decimal),
which stands for the program counter. These are special cases of
some more general modes we will learn later.
NOTE: In the VAX documentation and system software, the convention is
used that the bytes comprising an instruction are written from
RIGHT TO LEFT - so the operand specifier is always on the right
in the examples that follow.
a. REGISTER MODE - Mode = 5. The operand is found in the register
specified by Reg.
Example: 50 The operand is found in R0
Assembler syntax: Rn - Example: R0
b. ABSOLUTE MODE - Mode = 9; Reg = F (R15 = PC).
The next four bytes in the instruction stream contain the address
of the operand (so the total length of the operand specifier is 5)
Example: 00 00 04 00 9F The operand is found at location 400
Assembler syntax: @# address - Example: @#^X400
c. IMMEDIATE MODE - Mode = 8; Reg = F (R15 = PC).
The next 1-16 bytes in the instruction stream contain the actual
value of the operand (so the total length of the operand specifier
is 2-17). The number of bytes used depends on what kind of operand
the instruction calls for (byte, word, etc.)
Example (assume instruction needs a long-word operand)
00 00 04 00 8F The operand is 400
Assembler syntax: I^# value - Example I^#^X400
May be abbreviated to # value (e.g. #^X400) in some cases, though
this can also abbreviate another mode.
NOTE: Immediate mode can NEVER be used for the DESTINATION operand
of an instruction. This would entail modifying the actual
instruction being executed.
d. RELATIVE MODE - Mode = A, C, or E; Reg = F (R15 = PC)
The next 1 (Mode = A), 2 (Mode = C), or 4 (Mode = E) bytes in the
instruction stream contain an OFFSET that is to be added to the PC
to calculate the address of the operand.
- The PC value used is what is in the PC after the complete operand
specifier has been read
- This mode sometimes allows for shorter instructions than when
using absolute mode, and also supports POSITION-INDEPENDENT CODE.
Example: Assume the following operand specifier begins at location
400
20 AF The operand is found at 402 + 20 = 422
Example: (Same assumption)
00 40 00 00 EF The operand is found at 405 + 400000 =
400405
Assembler syntax: B^address, W^address, or L^address
Examples: B^^X422, L^^X400405
C. Some op-codes (see Programming Card p8 ff)
MOVB 90 (Two operands each - source and destination. Source is
MOVW B0 copied to destination )
MOVL D0
ADDB2 80 (Two operands each - source and destination. Source is
ADDW2 A0 added to destination.)
ADDL2 C0
SUBB2 82 (Two operands each - source and destination. Source is
SUBW2 A2 subtracted from destination.)
SUBL2 C2
MULB2 84 (Two operands each - source and destination.
MULW2 A4 Destination is multiplied by source.)
MULL2 C4
DIVB2 86 (Two operands each - source and destination. Source is
DIVW2 A6 divided into destination.)
DIVL2 C6
INCB 96 (One operand each - add one to destination)
INCW B6
INCL D6
DECB 97 (One operand each - subtract one from destination)
DECW B7
DECL D7
CLRB 94 (One operand - destination is set to zero)
CLRW B4
CLRL D4
III. An example:
A. Consider the following Pascal assignment statement, and assume that the
variables are longword integers located in memory as indicated:
W := X * Y + 3 * Z - 1 W is at 400
X is at 404
Y is at 408
Z is at 40C
B. This could be translated into machine language as follows. (Note that
we use R0 as a temporary when computing 3 * Z to avoid destroying the
original value of Z)
00 00 04 00 9F 00 00 04 04 9F D0 MOVL @#X, @#W
00 00 04 00 9F 00 00 04 08 9F C4 MULL2 @#Y, @#W
50 00 00 04 0C 9F D0 MOVL @#Z, R0
50 00 00 00 03 8F C4 MULL2 I^#3, R0
00 00 04 00 9F 50 C0 ADDL2 R0, @#W
00 00 04 00 9F D7 DECL @#W
(Total length = 49 bytes)
C. A shorter program could be written using relative mode addressing.
(Assume the program begins at address 3C0)
3B AF 41 AF D0 MOVL B^X, B^W
36 AF 40 AF C4 MULL2 B^Y, B^W
50 3F AF D0 MOVL B^Z, R0
50 00 00 00 03 8F C4 MULL2 I^#3, R0
27 AF 50 C0 ADDL2 R0, B^W
24 AF D7 DECL B^W
(Total length = 28 bytes)
Copyright ©1999 - Russell C. Bjork