CS222 Lecture: Other CPU Architectures: 0,1,2 and 3 address machines
Last revised 2/23/99
Introduction
------------
A. Recall that, at the start of the course, we drew a distinction between
computer ARCHITECTURE and computer ORGANIZATION.
1. An architecture is a functional specification of a computer system,
generally defined in terms of how the system is seen by an assembly
language programmer.
2. An organization a particular way of implementing an architecture.
B. For most of this semester so far, we have been studying in detail a
particular architecture: that of the VAX, often contrasting it with
a very different architecture: that of MIPS. After spring break, we will
move to a study of basic principles of computer organization. Before we
do this, though, we will spend some time looking at computer architectures
other than that of the VAX and MIPS.
1. It turns out that a computer architect faces a number of fundamental
choices in designing a CPU architecture. Different architectures
represent different combinations of these choice.
ASK CLASS: If you were designing a new CPU architecture, what
basic issues would you need to think about. (Recall that
a CPU architecture is basically the structure of a machine
as seen by an assembly language programmer.)
a. The set of data types that are to be directly supported by the
hardware.
b. The size of the logical address space the machine can access.
c. The set of programmer-visible registers that are used to store and
manipulate data.
d. The format of individual machine instructions.
e. The set of instructions that are provided in hardware.
f. The modes that are provided for generating the address of the
operands these instructions work on.
2. We will look at each choice individually.
I. Hardware data types
- -------- ---- -----
A. All CPU's provide for the manipulation of binary integers of some
specified number of bits (called the word length of the machine).
1. Word lengths for current architectures vary from 8 bits to 64 bits.
a. The earliest microprocessors used an 8 bit word, due to
technological reasons. Today's integrated circuit technology
permits 32 and 64-bit word lengths, but 8-bit word length
microprocessors are still used in applications (e.g. embedded
control systems) where a longer word length does not justify the
increased cost.
Example: the Z80
b. 16 bit word length CPU's were once fairly common, both in the
form of minicomputers (CPU's built from individual chips), and
as a technological step up from 8 bit microprocessors), but now if
the application calls for more than an 8 bit word the usual step
is to a 32 bit word length (although 16 bit CPU's are still made.)
Examples (historic): Intel 8086, 80186, 80286 (microprocessors)
DEC PDP-11 (minicomputer)
The chip used in the original IBM PC (Intel 8086/88) used a 16-bit
word, and prior to Windows 95 Microsoft's operating systems were \
based on this architecture, even when running on 32-bit chips.
c. From the 1960's onward, mainframe computers have used a 32-bit
word size. 32-bit microprocessors became possible during the
late 1980's. The most common word size for CPU's today is 32 bits.
d. There are also some 64-bit CPU's - e.g. DEC's Alpha, high end
members of the MIPS family, and Intel's Merced project (not yet
in production).
2. Many CPU's actually provide for the manipulation of several sizes of
binary integers - often 8, 16, 32 and perhaps 64 bits.
a. As we have noted, one of these sizes is typically designated as the
natural WORD SIZE of the machine, and governs the width of internal
registers, data paths etc. (E.g. 32 bits for the VAX).
b. Frequently, another size (generally the smallest one) is chosen as
the basic ADDRESSABLE UNIT, and represents the smallest piece of
information that can be transferred to or from a unique address in
memory.
i. On most modern machines, the addressable unit is the byte
ii. Many older machines, and some modern ones, are only word
addressable
iii. Some machines have been built that allow addressing down to the
individual bit.
c. The drawing of a distinction between the addressable unit and the
word size was an important technical innovation that first appeared
in the IBM 360 series (early 1960's). It allowed a single
architecture to be used for both business applications (which
typically work with byte-sized character data) and scientific ones
(that typically need long words for arithmetic.)
3. Of course, only one size is ESSENTIAL. Other sizes could be
synthesized in software by combining operations on adjacent data items
(to get a bigger size) or packing several smaller items into one word.
But doing such operations in software requires multiple instructions,
and so performance considerations generally dictate offering multiple
sizes in hardware.
B. Some CPU's provide for other data types - including some or all of the
following:
1. Binary bit vectors of varying length (not necessarily multiples of the
addressable unit.)
2. Decimal integers, represented using packed binary coded decimal (BCD)
or some other scheme.
3. Floating point numbers. (Sometimes provided for by a separate - and
optional - coprocessor chip in microprocessor-based systems.)
4. Character strings (arbitrary-length strings of bytes).
Example: The VAX supports all of the above, plus others.
C. The architect's choice of data types to be supported by the hardware has
a profound impact on the rest of the architecture.
1. The tendency in the 1980's was to move toward ever-richer sets of
hardware-supported data types. The VAX is really the epitomy of
this trend.
2. RISC's tend to support only the basic integer types (8, 16, 32
and maybe 64 bit) with a floating point coprocessor used for
floating point numbers and all other data types managed by software
using these basic types.
II. Size of the Address Space
-- ---- -- --- ------- -----
A. As we have seen, many instructions have to refer to one or more operands
contained in memory. One key architectural question is the length, in
bits, of the address of an item in memory, because this determines the
size of the logical address space the CPU can address, and hence how much
memory can be used.
Example: the IBM 360/370 series was originally designed to use a 24
bit address, limiting the address space to 16MB. At the time the
architecture was designed (early 1960's), this seemed an
exceedingly generous figure; but it has since become a key
limitation that has led to a need to significantly modify the
architecture.
B. Often, the address size is the same as the word size, because addresses
are often calculated using integer arithmetic operations.
1. Example: PDP-11 - 16 bit word, 16-bit address
2. Example: VAX, MIPS, many others: 32 bit word, 32-bit address
C. However, some machines have address sizes smaller than the word size or
larger than the word size. The latter requires some tricky mechanisms to
allow the formation of an address.
1. Example: IBM 360/370 - 32 bit word, but 24 bit address
2. Example: Intel 8086/8088 etc. - 16 bit word, but 20 bit address. (All
addresses are formed using a 16 bit offset relative to a 16 bit
segment register that is internally shifted left 4 places.)
III. Register sets
--- -------- ----
A. Early computers - like the VonNeumann machine - generally provided only
a single register that could be directly manipulated by the assembly
language programmer - normally called the accumulator.
B. However, as hardware costs dropped it became obvious that having more
than one such register would be advantageous.
1. Data that is stored in a register can be accessed much more quickly
than data stored in memory, so having multiple registers allows the
subset of a program's data items that is currently being manipulated
to be accessible more quickly.
2. Modern CPU's typically have anywhere from a half dozen to 32 more or
less general purpose registers (plus other special purpose ones.)
3. In fact, some CPU's have been built with as many as 256 registers!
4. However, there are some microprocessors (e.g. the 6502) that have
the one accumulator register structure inherited directly from
the VonNeumann machine.
C. One question is how functionality should be apportioned among the
programmer-visible registers. Here, several approaches can be taken.
1. Multiple registers, each with a specialized function - e.g.:
- AC (accumulator)
- MQ (multiplier-quotient: extends the AC for multiply/divide)
- Base register - one or several
- Index register - one or several
Examples: Many micros
- Z80: A register = accumulator; B..E = temporary storage;
IX,IY = index.
- 8086/88: AX = accumulator; BX, CX, DX can also be used as
accumulators, but not as flexibly; BX, BP can be used as
base registers; SI, DI - index registers. [IBM PC]
2. Multiple general-purpose registers - often designated R0, R1 ....
Example: Many modern machines including the VAX and MI{S
3. A hybrid approach, with multiple general registers for arithmetic, etc.
and multiple address registers for forming addresses.
Example: Motorola 680x0
4. A very large number of general registers, organized into smaller sets -
only one of which is "visible" at a time. (This allows each procedure
in a sequence of procedure calls to have its own private set of
registers).
Example: Berkeley RISC
5. At the opposite extreme, it is possible to design a machine with NO
programmer visible registers per se, by using a stack architecture
in which all instructions operate on a stack maintained by the
hardware.
Example: Java Virtual Machine
D. In deciding on a register set architecture, there is an important trade
off. When a machine has multiple registers, each instruction must
somehow designate which register(s) is/are to be used. Thus, going from
one AC to (say) 8 registers adds 3-9 bits to each machine language
instruction - depending on how many register operands must be specified.
IV. Instruction Formats
-- ----------- -------
A. Different computer architectures differ quite significantly in the
format of instructions. Broadly speaking, they can be classified into
perhaps four categories, by looking at the format of a typical
computational instruction (e.g. ADD). To compare these architectures,
we will look at how they implement two HLL statements:
Z := X + Y
Z := (X + Y)/(Q - Z)
B. Memory-memory architectures: all operands of a computational instruction
are contained in memory.
1. Three address architecture: op source1 source2 destination
(or op destination source1 source2)
Z := X + Y
ADD X, Y, Z
Z := (X + Y)/(Q - Z)
ADD X, Y, T1
SUB Z, Q, T2
DIV T2, T1, Z
Example: VAX ...3 instructions
2. Two address architecture: op source destination
(or op destination source)
(destination serves as both the second source and the destination)
Z := X + Y
MOV X, Z
ADD Y, Z
Z := (X + Y)/(Q - Z)
MOV Q, T1
SUB Z, T1
MOV X, Z
ADD Y, Z
DIV T1, Z
Example: VAX ...2 instructions
3. Note that the VAX is unusual in having both formats
4. Multiple register machines generally allow registers to be
used in place of memory locations, as on the VAX.
B. Memory-register architectures: one operand of an instruction is
in memory; the other must be in a register. Note: These are often
called "one address" architectures.
1. Multiple register machine: op source register
(The designated register serves as both the second source and
the destination; on some machines (e.g. Intel 80x86), the
memory location may also serve as the destination.)
(Multiple register machines generally allow a register to be used
instead of the memory operand, as well)
Z := X + Y
LOAD X, R1
ADD Y, R1
STORE R0, Z
Z := (X + Y)/(Q - Z)
LOAD X, R1
ADD Y, R1
LOAD Q, R2
SUB Z, R2
DIV R2, R1
STORE R1, Z
Example: Intel 80x86
2. Single accumulator machine: op source
(AC serves as both the second source and destination)
Z := X + Y
LOAD X
ADD Y
STORE Z
Z := (X + Y)/(Q - Z)
LOAD Q
SUB Z
STORE T1
LOAD X
ADD Y
DIV T1
STORE Z
Example: The Z80
C. Load-store architecture: All operands of a computational instruction
must be in registers. Separate load and store instructions are
provided for moving a value from memory to a register (load) or
from a register to memory (store).
Z := X + Y
LOAD X, R1
LOAD Y, R2
ADD R1, R2, R1
STORE Z, R1
Z := (X + Y)/(Q - Z)
LOAD X, R1
LOAD Y, R2
ADD R1, R2, R1
LOAD Q, R2
LOAD Z, R3
SUB R2, R2, R3
DIV R1, R1, R2
STORE R1, Z
Example: RISCs, including MIPS
D. Stack architecture: All operands of a computational instruction
are popped from the runtime stack, and the result is pushed back on
the stack. Separate push and pop instructions are provided for moving
a value from memory to the stack (push), or from the stack to a
register (pop).
Z := X + Y
PUSH X
PUSH Y
ADD
POP Z
Z := (X + Y)/(Q - Z)
PUSH X
PUSH Y
ADD
PUSH Q
PUSH Z
SUB
DIV
POP Z
Example: Java Virtual Machine
E. As the examples above have noted, many machines allow the programmer
to choose between several formats.
1. VAX: Three address versus two address formats; and any operand can
be either a register or memory
2. IBM 360/370, 80x86: one operand can be either memory or a register;
the other must be a register.
3. Of course, this requires one or more additional bits in the op-code
to specify the format!
F. There appears to be a trend in terms of program length in the above
examples.
1. The example programs for the 3 address machine used the fewest
instructions, and those for the load-store and stack machines used
the most, with the other architectures in between. (This is a general
pattern.)
2. However, the program that is shortest in terms of number of
instructions may not be shortest in terms of total number of BITS -
because encoding an address in an instruction requires a significant
number of bits.
3. You will investigate this further on a homework set.
V. Instruction Sets
- ----------- ----
A. Every machine instruction includes an operation code (op-code) that
specifies what operation is to be performed. The set of all such
possible operations constitutes the INSTRUCTION SET of a machine.
B. Early computers tended to have very limited instruction sets: data
movement, basic integer arithmetic operations (+, -, *, and / - but
sometimes only + and -); integer comparison; bitwise logical and/or;
conditional and unconditional branch, subroutine call/return, IO
operations and the like.
C. Introducing multiple data types increases the size of the instruction
set, since there must be a version of each operation for each (relevant)
data type.
D. In thhe late 1970's and 1980's machines moved in the direction of
including some very complex and high-power instructions in the
instruction set. The VAX is one of the best examples of this trend,
with single machine-language instructions for operations like:
1. Character string operations that copy, compare, or search an entire
character string of arbitrary length using a single instruction.
2. Direct support for higher-level language constructs like CASE, FOR,
etc.
3. Complicated arithmetic operations such as polynomial evaluation.
4. Queue manipulations to or remove an item from a queue.
etc.
E. RISC architectures arose from a questioning of the wisdom of this trend,
leading to much simpler instruction sets.
1. The existence of complex instructions imposes a performance penalty
on all the instructions in the instruction set - for reasons that
will become more evident later.
2. On the other hand, if the instruction set is kept simple, the door
is opened to significant speed-up by the use of pipelining - i.e.
executing portions of two or more instructions simultaneously.
VI. Addressing Modes
-- ---------- -----
A. All architectures must provide some instructions that access data in
memory - either as part of a computational instruction, or via separate
load/store or push/pop instructions. A final architectural issue is
how is the address of a memory operand to be specified?
B. The set of addressing modes on the VAX represents the most inclusive
answer to this question. Most machines include only a subset of all
the possible modes. The following are quite common:
Immediate
Absolute
PC Relative
Register indirect (deferred)
Register + displacement
C. In keeping with the RISC philosophy, RISCs typically have a smaller
subset:
Immediate - often for just some instructions
Register + displacement (yields register indirect with displacement = 0)
PC Relative (some RISCs - but only for branches on MIPS)
Copyright ©1999 - Russell C. Bjork